The LPC11U68 micro-controller is a middle size micro-controller from the NXP LPC11U6x family. The LPC11U68 has 64 pins (manufacturer part number LPC11U68JBD64E) and it is the heart of the EigerDB starting level development board EigerDB Zero+.
The development board is used as teaching equipment in EigerDB payable tutorials together with free manuals. It is a 32-bit Microcontroller based on ARM Cortex-M0+ core. It can operate at a maximum frequency of 50 MHz. The core is using a two-stage pipeline and fast single-cycle I/O access.
The LPC11U68 specifications are:
- ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC)
- AHB multilayer matrix
- System tick timer
- Serial wire debug (SWD) and JTAG boundary scan modes supported
- Micro trace buffer (MTB) supported
- Flash in-application programming (IAP) and In-system programming (ISP
- 32-bit Integer division routines
- Simple DMA engine with 16 channels and programmable input triggers
- Pin interrupt and pattern match engine using eight selectable GPIO pins
- Two GPIO group interrupt generators
- CRC Engine
- Windowed watchdog timer (WWDT)
- Real-time clock (RTC) in the always-on power domain
- USB 2.0 Full-speed device controller with on-chip PHY. XTAL-less low-speed mode supported
- 12 MHz Internal RC oscillator trimmed to 1 % accuracy
- Flash in-application programming (IAP) and In-system programming (ISP
- 32-bit Integer division routines
- Simple DMA engine with 16 channels and programmable input triggers
- Pin interrupt and pattern match engine using eight selectable GPIO pins
- Two GPIO group interrupt generators
- 32 kHz On-chip oscillator for RTC
- Crystal oscillator with an operating range of 1 MHz to 25 MHz
- Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz
- PLL allows CPU operation up to the maximum CPU rate
- Second, dedicated PLL is provided for USB